1. Technical Field
This application relates in general to system level testing of interconnects for signal integrity, and in specific to the testing of particular parameters under substantially authentic conditions, thus allowing the determination of the effects on the signal and noise margins from specific design factors.
2. Background
In the past, the determination of how parameters were affecting signal integrity and noise margins for systems was typically accomplished by an estimation technique involving reduction and extrapolation. First, the chip, or a problem area of the chip, is reduced down to a very simple case, typically reducing the chip to only a handful of pins under very controlled circumstances. The reduction allows simulation of the chip circuitry. Next, the results of the simulation are then extrapolated from the narrow reduction focus of a few pins, to a more general case which has a higher pin count, e.g. the whole chip or the problem area.
This approach works well for a number of years. However, over time, the industry has evolved, so that the number of pins on a chip has substantially increased as the complexity of the chips has increased. Moreover, the amount of current and number of outputs that are being switched have grown exponentially over time. This has resulted in the inability of the estimation technique to produce a simulation that can be extrapolated into a model that is close enough to the real chip system to provide a meaningful result for the signal and noise margin measurements.
The estimation approach uses the symmetry and the geometry of the actual high pin count device as a pattern for the reduction and subsequent extrapolation. Thus, the high pin count device is be reduced down to a single quadrant of pins, and then the area is narrowed even further down to the smallest symmetrical portion that can be found. This makes the problem simple enough to allow for simulation. The simulation would be run on only that small subset portion, and then the result would be extrapolated to yield a result for the entire chip or a larger area of the chip.
This approach has two problems. First, the approach simplifies the problem to the extent that accurate results are not possible, and second, the approach isolates or limits the evaluation to only a single problem. For instance, with the problem of cross-talk, by reducing a chip down to a very small portion and examining only cross-talk, other related effects that can contribute to cross-talk or co-act with cross-talk to form a combined worse case, such as ground bounce or ground plane collapsing, are ignored and not reflected in the computed results.
Therefore, the combined effects of these problems would be missed when extrapolating up from the simple model, and this introduces a great deal of error because realistic representations are not being produced of the timing relationships for the events. Thus, an accurate reflection of the combined total event and its impact on the system performance is not obtained.
Most often, overly pessimistic results are obtained. A system designed from these results would under utilize the technology capabilities, and would have larger margins than necessary. The system may under perform as compared to other systems. To compensate for this, based from experience, the designers knowing that the system can actually be pushed harder than is indicated by the analysis, will attempt to do so by guessing or estimating what a realistic result would be. This approach often runs the risk of design failure, because a design is adopted that is more aggressive than is supported by simulation of data.
Also, overly optimistic results may be obtained from the test procedure discussed above. A system designed from these results would over utilize the technology capabilities, and would have little or no margins, and possibly even negative margins. The system may become unstable and fail frequently. Again, the designers, knowing this from experience, will take a more conservative approach which leads to using larger design margins to cover for the inaccuracies. This scenario results in an end-product which is not as competitive as it should be in the market because of overcompensation due to the inaccuracies.
Therefore, the estimation approach does not produce accurate results, and forces designers to make approximations as to the true values of the system. The estimation approach will not flag a problem where a problem is known to exist. So this approach has begun to breakdown because of the rising complexity of the chips and their pin counts.
These and other objects, features and technical advantages are achieved by a system and method which uses a test chip that has plurality of individually programmable input/output (I/O) circuits.
The invention that is described herein allows a circuit on the test chip to be programmed individually for I/O function and, by virtue of replication of this circuit many times across the test chip, event patterns can be created for simultaneously switching outputs (SSO) or receiving patterns can be created for simultaneously switching inputs (SSI) that represent real usage of a very high pin Application Specific Integrated Circuit (ASIC) device.
The invention allows flexibility to tailor the testing strategy at test time in the lab, in real time, and to create situations for testing to investigate any pin on the device transitioning in the presence of patterns of other I/O locations that are changeable on the fly. This allows the tester to perform a much richer test and a much more complete investigation into the combinational effects of these type of events and how they impact the design margins for signal and noise margins, e.g. for cross-talk, ground bounce, and signal integrity concerns. This approach achieves a clearer picture of the actual design margins are by category, incorporating the interaction of these various effects, and producing a set of summary restrictions for the real design process. This process allows the designer to achieve a set of design rules to be used on the final design which represents the best combination of necessary risks versus margins in the design to enable a balanced design to be realized with greater performance.
The chips of today use a design that has a multilevel interconnect, where there is an IC chip on a package which provides a second level interconnect, which is then socket or solder ball mounted onto a board which provides the first or main interconnect layer. The invention allows for the investigation of interactions at each layer of interconnect. For example, the cross-talk at the chip interconnect layer level or the second level interconnect level can be investigated by separating out the different effects through the choices of the I/O locations made to be the victim (cross-talk receiver) and made to be the talker (cross-talk sender). Additionally, cases can be chosen or combined to determine where the worst cases for cross-talk are located due to physical proximity on each of the layers. This enables the designer to receive an overall view of cross-talk under worst case conditions and to break that number down by repeated measurements under different conditions. The designer can determine the component contributions from each level of interconnect.
This provides the designer with a better understanding of all the contributory factors of where problems might exist, and then discloses a clear suggestion of which solution may be the best in terms of improving the performance of the package interconnect to avoid problems in the future to achieve a proper margin as might be required by an individual design.
This is a very uncomplicated approach. There are two reasons why it is important for the approach to be uncomplicated. The first is time, in that, a test chip is completed in the time between when a design program is embarked on and when the physical designs for the actual final system are committed to market. Therefore, any testing on a test chip must be performed within that time frame. Thus, the approach must be uncomplicated and easily implementable to produce results with a minimum overhead and delay. This is because the information that is being produced is fed back into the design process for the final system, which is time critical. Thus, more complex and ornate testing solutions do not provide the quick turn around that is required to be able to rapidly implement the test chip and then obtain useable data from it. Therefore, one of the goals for this invention is to keep it straightforward, so that the control logic, the board design, and the data and measurement processes could all be executed in the time necessary to achieve the feedback to the final system design and thus, the system could then be on target for its time to market cycle.
The second reason is that the testing involves timed events. One of the tests attempts to create a simultaneous event, and in order to do that, the testing circuits need to be highly replicated without variability. This inventive approach achieves such a result in that it provides a very uniform launch of simultaneous switching output and a very uniform capture of simultaneous switching input which supplies the overall current surge profile that is necessary to determine an accurate worst case in the design.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.